Holistic framework combining analog/mixed-signal computing, in-memory architectures, and ultra-high-speed interconnects.
Architectures and macros that reduce data movement by co-locating storage and computation. Research emphasizes mixed-signal and time-domain interfaces, non-volatile memory technologies, and algorithm-aware design tradeoffs that enable scalable and energy-efficient compute fabrics.
Custom accelerator architectures for ANN and neuromorphic workloads, spanning circuit techniques, compute macros, and system-level integration. This direction includes mixed-signal and time-domain hardware approaches tailored for energy-efficient edge intelligence and next-generation AI systems.
Mixed-signal interfaces that translate information across voltage, current, digital, and time domains. Research includes both conventional and application-specific converter architectures, with emphasis on energy efficiency, calibration, and integration with sensing and compute macros.
Timing-generation and synchronization circuits for mixed-signal, compute, and high-speed link applications. Research focuses on robust clock synthesis, alignment, and distribution techniques that sustain performance under jitter, mismatch, and PVT variability.
Energy-efficient interface circuits for high-speed die-to-die and chip-to-chip communication in chiplet-based systems. Research includes signaling and receiver architectures, clock/reference generation and distribution, crosstalk-aware operation, and calibration techniques for robust communication over ultra-dense short-reach channels.
We exploit delay, phase, and temporal encoding to perform computation and data conversion with high energy efficiency.
We tightly integrate memory devices and mixed-signal circuits to enable scalable and efficient in-memory computing architectures.
We prioritize designs that translate into measurable silicon, emphasizing prototyping, validation, and realistic system constraints.
