Analog & Mixed-Signal Computing
Architectures and circuits that exploit timing as a computational primitive for energy-efficient sensing, conversion, and AI acceleration.
About Us
Analog/Mixed-Signal Research Group at the Technion
We investigate analog/mixed‑signal ICs for the AI era—ultra‑dense die‑to‑die links, AI hardware accelerators, data converters, and clocking circuits. Our work spans architecture, circuits, tape‑out, and silicon validation.
Device-to-System ApproachHolistic AMS research using novel circuit desgin techniques, with CMOS and beyond-CMOS technologies.
Energy-Efficient AI Hardware AI accelerators merging AMS computing, in-memory computing and short-reach high-speed links
Experimental FocusDefinition → Design → Prototyping → Experimental Validation
Research vision
Our Vision
To enable the next generation of energy-efficient intelligent systems through innovations in analog and mixed-signal hardware
In-memory Computing
Cross-layer exploration of memory-based compute fabrics using emerging devices, mixed-signal interfaces, and algorithm-aware design.
Short-Reach High-Speed Interconnects
Dense die-to-die and chip-to-chip links, clocking strategies, and energy-efficient transceivers for chiplet-era systems.
Highlights
AMSG at a Glance
Cross-layer methodology
From emerging devices and mixed-signal circuits to AI accelerators and chiplet interconnects, our research spans the full stack of intelligent hardware systems.
Experimental Research
We emphasize experimental research, validating new architectures through prototypes, experimental measurements, and real silicon implementations.
Energy-Efficient AI Hardware
We develop analog and mixed-signal architectures that dramatically reduce energy and data movement for machine learning and intelligent sensing systems.
Preview
Recent publications snapshot
2026
Reconfigurable Time-Domain In-Memory Computing Macro using CAM FeFET with Multilevel Delay Calibration in 28-nm CMOS
IEEE Transactions on Circuits and Systems I · in press
2026
Ferroelectric FET-based Reconfigurable Voltage-to-Time Converter in 28 nm CMOS
IEEE International NEWCAS Conference, 2026 · *Equal contribution
2025
Fast-Locking and High-Resolution DLL with Binary Search and Clock Failure Detection for Wide Frequency Ranges in 3-nm FinFET CMOS
IEEE Open Journal of the Solid-State Circuits Society
Join the group
Interested in circuits, AI hardware, or wireline links?
We are always looking for talented individuals to join our team.